單項(xiàng)選擇題

A customer has a 32-core Power 770 with 4 AIX partitions and 2 IBM i partitions. They want to improve network availability and allow for concurrent maintenance.
What will support the customer requirement at  least cost?()

A.Build the logical partition infrastructure based on 6 or more VLANs.
B.Build the logical partition infrastructure based on two or more IVEs.
C.Build the logical partition infrastructure based on Partition Mobility.
D.Build the logical partition infrastructure based on redundant VIO Servers.


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1.單項(xiàng)選擇題A Technical and Delivery Assessment (TDA) is a structured technical inspection of a completed solution design. After the inspection is complete, what deliverable can the customer expect?()

A.Verification of the expected performance of the new solution.
B.A document used by IBM manufacturing to build and ship the system solution.
C.An IBM Quality Assurance Certificate which is supplied to the customer with the system.
D.A list of actions that are recommended to reduce risk and create a successful implementation.

2.單項(xiàng)選擇題

A system is being designed with many LPARs which will be clients of dual VIO Servers. The VIO Servers  must be redundant so that, in the event of scheduled maintenance, the clients do not need to be shut down.
Which of these strategies could be used to ensure that the client LPARs continue to be able to use the network in the event of a VIO Server being shut down?()

A.Implement PowerHA SystemMirror on both VIO servers.
B.Configure Etherchannel between the client LPARs and the two VIO servers.
C.Configure Network Interface Backup between the two VIO servers and use each VIO server to access the  network.
D.Implement Shared Ethernet Adapter failover and have all client partitions access the network through the shared adapters.

3.單項(xiàng)選擇題

A customer is unsure how POWER7 processors can outperform POWER6 processors when the clock speeds are slower.
What contributes to the improved performance?()

A.Added Turbo memory switching
B.Removed internal OLTP limits
C.Moved L3 cache onto the chip
D.Increased DDR2 memory speeds

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